System for simulating electrical delay characteristics of logic

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364DIG2, 3649163, G06F 1531

Patent

active

053966155

ABSTRACT:
A timing simulation system has a layout pattern data storage portion, a data extracting portion, a process parameter storage portion, a gain coefficient calculating portion, an attendant capacitance supply portion, and a timing simulation executing portion. The gain coefficient calculating portion and the attendant capacitance calculating portion calculate gain coefficients and attendant capacitances peculiar to elements and wires from the circuit connection data extracted from layout pattern data of a logic circuit, and the gain coefficient supply portion and the attendant capacitance supply portion set the gain coefficients and the attendant capacitances. The timing simulation executing portion calculates the total load capacitance and the total gain coefficient with respect to a group of equipotential wires in which the signal value changes, calculates the transition time of the signal value on the wires based on the total load capacitance and the total gain coefficient, and executes timing simulation while using the transition time as a signal propagation delay time.

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