Method for manufacturing an insulating trench in a substrate for

Details Method for manufacturing an insulating trench in a substrate for Method for manufacturing an insulating trench in a substrate for

1995-06-07

1996-03-05

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 62, 437 63, 437160, H01L 2176

Patent

active

054967651

ABSTRACT:
For manufacturing an insulation trench in a SOI substrate wherein logic components and high-voltage power components are integrated, a trench extending down onto the insulating layer of the SOI substrate is etched. By providing the sidewalls of the trench with an occupation layer containing a dopant and by drive-out from the occupation layer, diffusion regions neighboring the trench are produced. After complete removal of the occupation layer, a silicon layer is produced and an insulation structure is formed in the trench by thermal oxidation.

REFERENCES:
patent: 4471525 (1984-09-01), Sasaki
patent: 4493740 (1985-01-01), Komeda
patent: 4513026 (1985-04-01), Miyamoto et al.
patent: 4666556 (1987-05-01), Fulton et al.
patent: 4666557 (1987-05-01), Collins et al.
patent: 4845054 (1989-07-01), Mitchener
patent: 4872947 (1989-10-01), Wang et al.
patent: 5008210 (1991-04-01), Chiang et al.
patent: 5084408 (1992-01-01), Baba et al.
patent: 5116779 (1992-05-01), Iguchi
patent: 5202279 (1993-04-01), Chung et al.
patent: 5314845 (1994-05-01), Lee et al.
Becker, "Low Pressure Deposition of Doped SiO.sub.2 by Pyrolysis of Tetraethylorthosilicate (TEDS)", J. Electrochem. Soc: Solid-State Science and Technology; vol. 134, No. 11; 1987; pp. 2923-2931.
Y. Ohata et al., "Dielectrically Isolated Intelligent Power Switch", IEEE 1987 Custom Integrated Circuits Conference, pp. 443-446.
N. Yasuhara et al., "SOI Device Structures Implementing 650 V High Voltage Output Devices on VLSIs", IEEE, IEDM 1991, pp. 141-144.
D. Widmann et al., "Technologie hochitegrierter Schaltungen", Springer-Verlag, pp. 80-83 & pp. 223-225.
Japanese Abstract, "Semiconductor Device and Manufacture Thereof", 61-90442, E-436, Sep. 12, 1986, vol. 10/No. 268, pp. 247-250.
Japanese Abstract, "Manufacture of Semiconductor Device", 62-76646, E-538 Sep. 8, 1987 vol. 11/No. 277, pp. 235-239.
Japanese Abstract, "Formation of Interelement Isolation Region of Semiconductor Device", 4-134844, E-1254 Aug. 26, 1992, vol. 16/No. 403, pp. 241-243.
K. Fujino et al., "Surface Modification of Base Materials for TEOS/O.sub.3 Atmospheric Pressure Chemical Vapor Deposition", 1046 Journal of the Electrochemical Society 139 (1992) Jun., No. 6, Manchester, NH, US, pp. 1690-1692.
A. Nakagawa et al., "500V Lateral Double Gate Bipolar-Mode MOSFET (DGIGBT) Dielectrically Isolated by Silicon Wafer Direct-Bonding (DISDB)", Extended Abstracts of the 20th (1988 international) Conference on Solid State Devices and Materials, Tokyo, 1988, pp. 33-36.
IBM Technical Disclosure Bulletin, "Sidewall Channel-Stop Doping For Deep-Trench Isolation of FET Devices", vol. 27, No. 10A, Mar. 1985, pp. 5501-5504.

Affiliated with

Also associated with

Rating

Method for manufacturing an insulating trench in a substrate for does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing an insulating trench in a substrate for, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing an insulating trench in a substrate for will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1412778