Method of making junction-isolated high voltage MOS integrated d

Details Method of making junction-isolated high voltage MOS integrated d Method of making junction-isolated high voltage MOS integrated d

1995-06-02

1996-03-05

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 50, 437919, H01L 21761

Patent

active

054967619

ABSTRACT:
An integrated device includes isolating regions of a first type of conductivity, each surrounding an epitaxial pocket of an opposite type of conductivity, and housing drain and source regions, and covered with an oxide layer housing gate regions and over which extend the source, drain and gate connections. For linearizing potential distribution at the epitaxial pocket--isolating region junction and close to the source regions beneath the connections, these regions are provided with a double chain of condensers embedded in the oxide layer and the terminal elements and the intermediate element of which are biased to predetermined potentials.

REFERENCES:
patent: 4358890 (1982-11-01), Heller et al.
patent: 4419812 (1983-12-01), Topich
patent: 4790630 (1988-12-01), Maurice
patent: 5053352 (1991-10-01), Kaiser

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