Semiconductor memory device with redundant memory and floatable

Details Semiconductor memory device with redundant memory and floatable Semiconductor memory device with redundant memory and floatable

1992-09-25

1995-03-07

Harvey, Jack B.

Excavating

365200, 365201, 36518902, 371 102, G11C 700, G11C 1140

Patent

active

053964993

ABSTRACT:
A semiconductor memory device provided with a first circuit for storing and accessing data and a second circuit for storing and accessing internal information is disclosed, wherein the data and the internal information, when delivered from the first circuit and the second circuit, respectively, are transmitted through a common data line to an output terminal. The feature is that the second circuit is provided with a code generating circuit for generating test codes representing the internal information, and is arranged between the first circuit and the output terminal. The second circuit is operable in two modes, in the first mode transmitting data read from the first circuit directly to the output port through the common data line without any intervention of the code generating circuit, in the second mode delivering the test codes to the common data line.

REFERENCES:
patent: 4908798 (1990-03-01), Urai
patent: 4914632 (1990-04-01), Fujishima
patent: 4984205 (1991-01-01), Sugibayashi
patent: 5034925 (1991-07-01), Kato
patent: 5097447 (1992-03-01), Ogawa
patent: 5179536 (1993-01-01), Kasa
patent: 5195057 (1993-03-01), Kasa
patent: 5233610 (1993-08-01), Nakayama
patent: 5267205 (1993-11-01), Hamada
patent: 5278839 (1994-01-01), Matsumoto
patent: 5301155 (1994-04-01), Wada
patent: 5303192 (1994-04-01), Baba
patent: 5327380 (1994-07-01), Kersh, III et al.

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