Integratable semi-conductor memory cell

Details Integratable semi-conductor memory cell Integratable semi-conductor memory cell

1978-08-30

1981-02-24

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307292, 307317A, 365155, G11C 1140, H03K 3286

Patent

active

042530342

ABSTRACT:
An integratable semi-conductor memory cell has two bipolar transistors which are identical to one another and which have their collectors connected in series with respective circuit parts having a non-linear current characteristic, the respective circuit parts being connected to a first electrical potential. The circuit parts are also connected to the base of the other respective transistor. One emitter of each of the transistors is provided for control by means of logic signals and the invention is particularly characterized in that the circuit part located between the collector of each one of the transistors and a switching point carrying the first electrical potential are selected in such a fashion that the slope dU/dI of the current-voltage characteristic will always be higher than the slope of the corresponding current values in the current-voltage characteristic of the pn-junctions of the emitter-base circuit of both transistors.

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patent: 4125877 (1978-11-01), Reinert
Wiedmann, "Monolithic Circuit with Pinch Resistor", IBM Tech. Discl. Bull., vol. 13, No. 9, pp. 2469; 2/1971.
Moore, "Schottky Barrier Diode Storage Cell"; IBM Tech. Discl. Bull."; vol. 14, No. 6, pp. 1683; 11/1971.
Beers et al, "Integrated Harper Cell"; IBM Tech. Discl. Bull."; vol. 18, No. 9, pp. 2875-2877; 2/1976.

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