Process of manufacture of split gate EPROM device

Details Process of manufacture of split gate EPROM device Process of manufacture of split gate EPROM device

1994-04-08

1995-03-07

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 49, 437228, H01L 21265

Patent

active

053957792

ABSTRACT:
Fabrication of a MOSFET comprises, forming a dielectric layer on a substrate and a sacrificial structure on portions of the dielectric layer, forming a first polysilicon layer over the sacrificial structure and other exposed surfaces of the device, patterning the first polysilicon layer and the dielectric layer by masking and etching to form a stepped electrode structure partially upon the sacrificial structure and partially upon the other exposed surfaces of the device, applying ion implantation into the substrate outside of the area covered by the stepped electrode structure, removing the sacrificial layer from the surface of the substrate and from beneath the stepped electrode structure leaving an overhanging surface of the stepped electrode structure, forming a second layer of dielectric material on the exposed surfaces of the stepped electrode structure and the substrate, and forming a second polysilicon layer over and under overhanging portions the second layer of dielectric material and the substrate.

REFERENCES:
patent: 4988635 (1991-01-01), Ajika et al.
patent: 5045488 (1991-09-01), Yeh
patent: 5242848 (1993-09-01), Yeh
"A 128K Flash EEPROM Using Double-Polysilicon Technology" IEEE J. Solid-State Circuits, vol. SC-22, No. 5, pp. 676-683 (Oct. 1987).

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