Programmable gain accumulator

Details Programmable gain accumulator Programmable gain accumulator

1990-07-26

1991-10-29

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 738

Patent

active

050620711

ABSTRACT:
A programmable digital gain accumulator is provided with a digital accumulator having approximately the same number of significant bits as the input data stream. The most significant bit of the input data stream is a sign bit coupled to a series cascade of flip-flops providing a selectable plurality of flip-flop delay times. The carry output of the accumulator is coupled to an input up/down counter having its output coupled to a multiplexor capable of selecting one of the carry outputs of the input up/down counter. The up or down count is controlled by the sign bit input from the sign bit delay circuit. The output of the multiplexor is inputted to an output up/down counter whose parallel output is the parallel synchronous digital gain command signal for direct use by a utilization device. The up or down count of the output up/down counter is controlled by a delayed sign input from the sign bit delay circuit.

REFERENCES:
patent: 4729110 (1988-03-01), Welles et al.
patent: 4808939 (1989-02-01), Kingston
patent: 4841552 (1989-06-01), Kingston

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