Levelized logic simulator with fenced evaluation

Details Levelized logic simulator with fenced evaluation Levelized logic simulator with fenced evaluation

1989-03-15

1991-10-29

Gruber, Felix D.

Boots, shoes, and leggings

364488, G06F 1560, G06F 1520

Patent

active

050620673

ABSTRACT:
A simulator for a levelized logic circuit reduces the number of evaluations required. The simulator associates certain lists of signals, called fences, with each component of a logic circuit. A fence is evaluated to determine whether it is active or inactive. Active fences contain signals which have charged since a previous evaluation. Components for active fences are then evaluated by the simulator. Fences are formed by starting with a seed set of signals. If all of the input signals to a component are in one or more fences, a final fence for a component is formed which is the union of the one or more fences. Only signals which can cause an output change on a component are included in fences.

REFERENCES:
patent: 4697241 (1987-09-01), Lavi
patent: 4775950 (1988-10-01), Terada et al.
patent: 4791593 (1988-12-01), Hennion
patent: 4815024 (1989-03-01), Lewis
Breuer: Functional Partitioning and Simulation of Digital Circuits, IEEE Transactions on Computers, vol. C-19, No. 11, Nov. 1970, pp. 1038-1046.

Affiliated with

Also associated with

Rating

Levelized logic simulator with fenced evaluation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Levelized logic simulator with fenced evaluation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Levelized logic simulator with fenced evaluation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1403979