Patent
1989-02-28
1991-10-29
Munson, Gene M.
357 42, 357 67, 357 71, H01L 2904, H01L 2702, H01L 2348
Patent
active
050619837
ABSTRACT:
A method for manufacturing a semiconductor device that includes p- and n-type regions formed on an insulating substrate, and an interconnection layer electrically coupled with these p- and n-type regions. The interconnection layer is an n-type polycrystalline silicon layer which is electrically coupled with the p- and n-type regions through a metal silicide film formed between the interconnection layer and the p- and n-type regions.
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Edel et al., "Planarization of Metal Layers for Interconnections on Integrated Circuits", IBM Technical Disclosure Bulletin, vol. 14, No. 12, May '72.
Murarka, "Refractory Silicides for Integrated Circuits", J. Vac. Sci. Tech., 17(4) Jul./Aug. 1980.
Okada et al., "A New Polysilicon Process for a BiPolar Device-PSA Technology," IEEE Transactions on Electron Devices, vol. ED-26, No. 4, Apr., 1979, pp. 385-389.
Egawa Hideharu
Maeguchi Kenji
Nishi Yoshio
Munson Gene M.
Tokyo Shibaura Denki Kabushiki Kaisha
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