Gate array device

Details Gate array device Gate array device

1988-10-17

1990-07-31

Popek, Joseph A.

Static information storage and retrieval

Format or disposition of elements

365 63, 36518908, G11C 510

Patent

active

049455133

ABSTRACT:
A gate array device having an independent memory array region is disclosed. Only memory cells are disposed in the memory array region. Peripheral circuits for accessing the memory arrays such as an address decoder, sense amplifier and address buffer are formed of basic cells in a basic cell region. The unique arrangement of the gate array device permits a flexible selection of word and bit length of the memory array and an effective use of the memory array region.

REFERENCES:
patent: 4562453 (1985-12-01), Noguchi et al.
patent: 4791607 (1988-12-01), Igarashi et al.
Toshi Sano et al., "A 20ns CMOS Functional Gate Array with a Configurable Memory", 1983 IEEE International Solid-State Circuits Conference, pp. 146-147.
H. Tago et al., "A CMOS Gate Array with Easily Testable Three Port RAMs", 1984 IEEE (ICCD 1984), pp. 424-427.
Isao Ohkura et al., "A CMOS Gate Array for Computer Applications", 1983 IEEE (ICCD 1983), pp. 268-271.
Tomoku Takada, Haruyuki Tago, Masasumi Shiochi, "A CMOS Gate Array with RAMs", 1984 International Solid-State Device Conference (SSD 84-59), pp. 23-28.
Bowers, Stephen Glen, "CMOS Dual Port RAM Masterslice", IEEE 1982, (1982) CICC), pp. 311-314.

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