Memory controller with interleaved queuing apparatus

Details Memory controller with interleaved queuing apparatus Memory controller with interleaved queuing apparatus

1980-10-31

1984-05-29

Chan, Eddie P.

Boots, shoes, and leggings

G06F 1300

Patent

active

044518803

ABSTRACT:
A memory controller controls the operation of a number of memory module units and includes a number of queues which couple to the module units. Each queue includes an address queue register, a control queue register and a data queue register. Each address queue register has tristate control for independent operation. Control circuits which couple to the queue address, control and data registers assign memory cycles between queues on an alternate basis when the queue control registers store requests which are being processed. This enables the interleaving of memory requests which eliminates processing delays particularly in cases where such requests involve multiword transfers over successive memory cycles of operation.

REFERENCES:
patent: 3735354 (1973-05-01), Delaney et al.
patent: 3961312 (1976-06-01), Bodner et al.
patent: 4000485 (1976-12-01), Barlow et al.
patent: 4151598 (1979-04-01), Webster
patent: 4281381 (1981-07-01), Ahuja et al.
IBM Tech. Discl. Bulletin, vol. 17, No. 9, Feb. 1975, T. H. Miller et al., "Interleaved Cycle Steal Burst Circuitry", pp. 2732-2735.

Affiliated with

Also associated with

Rating

Memory controller with interleaved queuing apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory controller with interleaved queuing apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory controller with interleaved queuing apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1401097