Circuit for speeding up a read operation from a ROM, the ROM ser

Details Circuit for speeding up a read operation from a ROM, the ROM ser Circuit for speeding up a read operation from a ROM, the ROM ser

1994-09-27

1997-01-14

Moore, David K.

395496, G06F 1300

Patent

active

055948880

ABSTRACT:
The present invention is to improve the processing capability of a micro processor by speeding up a read operation of program memory stored in a ROM. The present invention comprises a first ROM for storing program data corresponding to even-numbered addresses and a second ROM for storing program data corresponding to odd-numbered addresses. It further comprises an address generator circuit for adding +1 to an address indicated by A1 - An when a least significant address bit A0 is 1. Hereby, when a present read operation is done for an odd-numbered address, an even-numbered address next to the foregoing odd-numbered address is simultaneously read to speed up read operation from a ROM.

REFERENCES:
patent: 4086629 (1978-04-01), Desyllas et al.
patent: 4319324 (1982-03-01), Johnson et al.
patent: 4378591 (1983-03-01), Lemay
patent: 4424561 (1984-01-01), Stanley et al.

Affiliated with

Also associated with

Rating

Circuit for speeding up a read operation from a ROM, the ROM ser does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit for speeding up a read operation from a ROM, the ROM ser, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for speeding up a read operation from a ROM, the ROM ser will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1395788