PCI split transactions utilizing dual address cycle

Details PCI split transactions utilizing dual address cycle PCI split transactions utilizing dual address cycle

1995-01-04

1997-01-14

Harrell, Robert B.

G06F 1200

Patent

active

055948820

ABSTRACT:
A scheme for providing split transaction capability on a PCI standard bus without modification to the existing PCI standard. Additional address bits are provided to a standard PCI address signal. The additional bits carry information regarding the requestor of a read transaction. By providing the requestor's identification to an addressed target, data is provided by the target device as a posted write. By using this enhanced mode, read requests need not be continually retried. If a target device is unable to respond to the enhanced address signal, the transaction is resent as a standard PCI address signal with the enhanced bits turned off.

REFERENCES:
patent: 5283904 (1994-02-01), Carson et al.
patent: 5321818 (1994-06-01), Wendling et al.
"The Metaflow Architecture", IEEE Micro., by Val Popescu, Merle Schultz, John Spracklen, Gary Gibson, Bruce Lightner and David Isaman, 1991.

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