Multiplex communications – Wide area network – Packet switching
Patent
1995-03-21
1997-01-14
Pan, Daniel H.
Multiplex communications
Wide area network
Packet switching
395877, 370389, 370230, G06F 1314, G06F 1516, G06F 15163
Patent
active
055948685
ABSTRACT:
A parallel processor system includes: a reception buffer pointer controller for generating an address of a reception buffer area in which a received packet is written and for checking whether there is no space area in the reception buffer area; a discard command bit capable of being set and reset by an instruction processor; a received packet discard judging unit for judging from the discard command bit and information supplied from the reception buffer pointer controller, whether the received packet is written, suspended, or discarded; and a reception controller for controlling to write the received packet in the reception buffer area in accordance with an judgement by the received packet discard judging unit. With this arrangement, even if there is no space area in the reception buffer area for storing a received packet or even if the received packet cannot be received because of a failure in the reception processor unit, the received packet can be discarded at the reception processor unit.
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Ando Toshimitsu
Higuchi Tatsuo
Iwasaki Masaaki
Kato Shin-ichi
Nakagoshi Junji
Hitachi , Ltd.
Pan Daniel H.
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