Communicating adder tree system for neural array processor

Details Communicating adder tree system for neural array processor Communicating adder tree system for neural array processor

1991-08-05

1992-09-08

Mai, Tan V.

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364786, 395 27, G06F 752

Patent

active

051464209

ABSTRACT:
The neural computing paradigm is characterized as a dynamic and highly computationally intensive system typically consisting of input weight multiplications, product summation, neural state calculations, and complete connectivity among the neurons. Herein is described neural network architecture for a Scalable Neural Array Process (SNAP) which uses a unique intercommunication scheme within an array structure that provides high performance for completely connected network models such as the Hopfield model. SNAP's packaging and expansion capabilities are addressed, demonstrating SNAP's scalability to larger networks. The array processor uses a special type of adder tree which computes in a first direction and communicates in a second direction. The adder tree is thus responsive to a compute state and a communication state. The adder tree has the ability to provide a first driver responsive to a compute state for communicating an adder output to a data path and a second driver responsive to the communication state for connecting the data path to the neuron inputs.

REFERENCES:
patent: 4891782 (1990-01-01), Johnson
patent: 5040134 (1991-08-01), Park
"Parallel Distributed Processing vol. 1: Foundations" Cambridge, Mass.: MIT Press 1986, pp. 45-76, 319-362. D. E. Rumelhard, J. L. McClelland and the PDP Research Group.
"Neurons with Graded Response have Collective Computational Properties like those of Two-State Neurons" J. J. Hopfield Proceedings of Nat'l Acad. of Sci 81, pp. 3082-3092, May 1984.
"A Unified Systolic Architecture for Artificial Neural Networks" S. Y. Kung and J. N. Hwang, Journal of Parallel and Distributed Computing 6, pp. 358-387, 1989.

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