Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Patent
1996-04-01
1998-06-23
Powell, William
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
With electrical circuit layout
438 14, H01L 2100
Patent
active
057704813
ABSTRACT:
A wiring designing apparatus and a wiring designing method is provided that comprise a wiring region setting unit for inputting a net list containing the nets for terminal connections and for setting a channel wiring region for wiring. A partial channel setting unit sets a partial channel region in the channel wiring region. A net selecting unit selects target nets for wiring designing from the net list, and a virtual terminal setting unit sets necessary virtual terminals on the boundaries of the partial channel region. A trunk allocating unit allocates the trunks of the selected nets to the wiring tracks in the partial channel region, and a wiring inhibited pattern updating unit outputs the wiring results after an update of the wiring inhibited pattern corresponding to the results of the trunk allocation by the trunk allocating unit. A net list updating unit updates the net list corresponding to the results of the trunk allocation by the trunk allocating unit.
REFERENCES:
patent: 4974048 (1990-11-01), Chakravorty et al.
patent: 5264390 (1993-11-01), Nagase et al.
patent: 5565386 (1996-10-01), Bearden et al.
NEC Corporation
Powell William
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