Synchronous semiconductor memory device

Details Synchronous semiconductor memory device Synchronous semiconductor memory device

1995-04-10

1997-01-14

Popek, Joseph A.

Static information storage and retrieval

Addressing

Sync/clocking

36523003, 365195, 365203, G11C 800

Patent

active

055947042

ABSTRACT:
Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed. A synchronous semiconductor memory device having small chip area, high speed of operation, low power consumption and multiple functions is provided.

REFERENCES:
patent: 4612631 (1986-09-01), Ochii
patent: 4796224 (1989-01-01), Kawai et al.
patent: 4953131 (1990-08-01), Purdham et al.
patent: 5083296 (1992-01-01), Hara
Nikkei Electronics, Feb. 3, 1992, p. 85.

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