Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1996-04-16

1997-05-13

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Sync/clocking

36523006, 365236, G11C 800

Patent

active

056299036

ABSTRACT:
This invention discloses a synchronous DRAM. An address counter provides a column address of eight bits. The low-order four bits of the column address are assigned to a first column predecoder while the high-order four bits are assigned to a second column predecoder. The first column predecoder provides first predecode signals which are activated in synchronization with a clock leading edge of an internal clock signal and deactivated in synchronization with a clock trailing edge subsequent to the clock leading edge. The second column predecoder provides second predecode signals which make a transition in synchronization with the clock trailing edge. A column decoder sequentially activates column-select lines of a memory cell array according to the AND obtained from all combinations of the first predecode signals and the second predecode signals. Fast, low power column-select line activation is accomplished accordingly.

REFERENCES:
patent: 4931998 (1990-06-01), Ootani et al.
patent: 5119334 (1992-06-01), Fujii
patent: 5357479 (1994-10-01), Matsui
patent: 5566119 (1996-10-01), Matano
Fujiwara et al., "A 200MHz 16Mbit Synchronous DRAM with Block Access Mode", 1994 Symposium on VLSI Circuits Digest of Technical Papers, pp. 79-80.

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