Method for making MOSFET device having controlled parasitic isol

Details Method for making MOSFET device having controlled parasitic isol Method for making MOSFET device having controlled parasitic isol

1996-10-28

1998-03-10

Niebling, John

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Field plate electrode

438294, 438585, H01L 2144

Patent

active

057260958

ABSTRACT:
A MOSFET has shallow trenches of a thick oxide for isolating the MOSFET device from a surrounding substrate. The MOSFET has a gate wiring layer that includes co-aligned metallurgy of a predetermined work function at regions where the gate wiring layer passes over the oxide of the isolation trenches. The co-aligned metallurgy of predetermined work function is operative to increase the parasitic threshold voltage associated with the MOSFET's parasitic leakage currents.

REFERENCES:
patent: 5451546 (1995-09-01), Grubisich

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