Phase lock loop having a reduced synchronization transfer period

Details Phase lock loop having a reduced synchronization transfer period Phase lock loop having a reduced synchronization transfer period

1995-08-03

1997-05-13

Pascal, Robert

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular frequency control means

331 57, 331 14, 331 17, 331DIG2, 327158, 375376, H03L 7095, H03L 7099

Patent

active

056296517

ABSTRACT:
A phase lock loop has a lock detection circuit, a phase comparator, a charge pump circuit, a low-pass filter, a variable delay circuit and a frequency divider. The lock detection circuit generates a lock detection signal when a phase difference between an input reference clock and an output of the variable delay circuit is smaller than a predetermined value in a first stage of the synchronization operation. The input and output of the variable delay circuit are connected in a loop responding to the lock detection signal to form a voltage controlled oscillator (VCO) and shift the phase lock loop into a second stage of the synchronization operation. An initial control signal for controlling the VCO in the second stage is obtained as a value of the variable delay circuit in the first stage before generation of the lock detection signal, thereby obtaining a higher-speed synchronization operation and low jitters in the output clock.

REFERENCES:
patent: 5173617 (1992-12-01), Alsup et al.
patent: 5210509 (1993-05-01), Greef et al.
patent: 5220294 (1993-06-01), Ichikawa
patent: 5260979 (1993-11-01), Parker et al.
patent: 5389898 (1995-02-01), Taketoshi et al.
patent: 5463337 (1995-10-01), Leonowich
Hideo Sato et al., "A Fast Pull-In PLL IC Using Two-Mode Pull-In Technique", Electronics and Communications in Japan, Part 2, vol. 75, No. 3, 1992, pp. 41-51.

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