Microprocessor with reduced area coupling a register file with a

Details Microprocessor with reduced area coupling a register file with a Microprocessor with reduced area coupling a register file with a

1997-06-24

1999-06-29

Donaghue, Larry D.

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395391, 39580032, 364491, 364489, G06F 1300

Patent

active

059180650

ABSTRACT:
The parallel processing microprocessor includes a register file for storing a plurality of data and a plurality of groups of bit sliced circuits provided corresponding to a plurality of data. Each group of bit sliced circuits consists of a plurality of bit sliced circuits. The plurality of bit sliced circuits are arranged collectively. The plurality of bit sliced circuits are arranged corresponding to a plurality of instructions and processing in parallel a corresponding one of the plurality of data in response to the plurality of instructions.

REFERENCES:
patent: 4670846 (1987-06-01), Laws
patent: 4951221 (1990-08-01), Corbett et al.
patent: 5010511 (1991-04-01), Hartley et al.
patent: 5379257 (1995-01-01), Matsumura et al.
patent: 5493506 (1996-02-01), Sakashita et al.
patent: 5530661 (1996-06-01), Garbe et al.
"A 1,000MIPS BiCMOS Microprocessor with Superscalar Architecture", ISSCC Digest of Technical Papers, pp. 114-115, 260, Feb. 1992.

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