Semiconductor package utilizing edge connected semiconductor dic

Details Semiconductor package utilizing edge connected semiconductor dic Semiconductor package utilizing edge connected semiconductor dic

1990-10-05

1992-09-08

Jackson, Jr., Jerome

357 68, 357 65, H01L 2302

Patent

active

051463083

ABSTRACT:
Die bond locations on a semiconductor die are formed as vertical inserts along the edge of the die. The vertical inserts are isolated from substrate and are exposed by a wafer saw process, in which dice are singulated from a wafer. The configuration offers the advantages of a more efficient layout, allowing the entire top surface of the die to be passivated, a better contact configuration, and more convenient assembly for packaging.

REFERENCES:
patent: 3492536 (1970-01-01), Girolamo et al.
patent: 4697204 (1987-09-01), Mita et al.
patent: 4922378 (1990-05-01), Malhi et al.
"High Density Chip Carrier with Protected Leads", IBM TDB, vol. 31, No. 2, Jul. 1988, pp. 238-239.

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