Method for designing path transistor logic circuit

Details Method for designing path transistor logic circuit Method for designing path transistor logic circuit

1996-07-25

1999-06-29

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364489, G06F 1700, G06F 1750

Patent

active

059177284

ABSTRACT:
A method for designing a path transistor logic circuit based on a logic specification of a given circuit according to the present invention includes the steps of: generating a logic circuit including logic gates based on the logic specification, the logic circuit receiving input signals; evaluating signal transition probability of each of the input signals of the logic circuit; arranging the input signals of the logic circuit in a descending order of signal transition probability; generating a binary decision diagram corresponding to the logic circuit by applying Shannon expansion to the logic circuit in accordance with the descending order of signal transition probability, the binary decision diagram including nodes; and replacing each of the nodes of the binary decision diagram with a two-input selector circuit including a path transistor so as to obtain the path transistor logic circuit.

REFERENCES:
patent: 5210699 (1993-05-01), Harrington
patent: 5469367 (1995-11-01), Puri et al.
Yano et al, IEEE 1994 Custom Integrated Circuits Conf., pp. 603-606, 1994, "Lean Integration: Achieving a Quantum Leap in Performance and Cost . . . "
Malik et al, IEEE Proc. ICCAD '88. pp. 6-9, 1988, "Logic Verification Using Binary Decision Diagrams in a Logic Synthesis Environment."
Tsui et al; 30th ACM/IEEE Design Automation Conf., pp. 68-73, 1993, "Technology Decomposition and Mapping Targeting Low Power Dissipation."
Friedman et al. IEEE Transactions on Computers, vol. 39, No. 5, pp. 710-713, 1990, "Finding the Optimal Variable Ordering for Binary Decision Diagrams."
Berman et al. "Efficient Techniques for Timing Correction," IEEE, 1990, pp. 415-419.
Akita et al. "A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability," IEEE, 1994, pp. 420-424.
Yano et al. "Lean Integration: Achieving a Quantum Leap in Performance and Cost of Logic LSIS," IEEE, 1994, pp. 603-606.
Tsui et al. "Technology Decomposition and Mapping Targeting Low Power Dissipation," IEEE, 1993, pp. 68-73.

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