Multilevel instruction cache

Details Multilevel instruction cache Multilevel instruction cache

1994-04-08

1995-12-05

Lall, Parshotam S.

Boots, shoes, and leggings

36424342, 36424344, 3642632, 364DIG1, G06F 926, G06F 1200

Patent

active

054737648

ABSTRACT:
A cache memory for use between a processing unit and a main memory includes a prefetch buffer, a use buffer, and a head buffer. The prefetched buffer is a FIFO or LRU register which prefetches instructions from contiguous memory locations after the address specified by the program counter. The head buffer is a FIFO or LRU register which is utilized to store instructions from the tops of the program blocks which are accessed from main memory following recent cache misses. The use buffer is a relatively large, inexpensive buffer, preferably a directly mapped buffer, which stores recent hits from the prefetched buffer as well as selected instructions from main memory following cache misses.

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