Method and system for pipelining bus requests

Details Method and system for pipelining bus requests Method and system for pipelining bus requests

1994-01-25

1995-12-05

Harvey, Jack B.

395293, 395298, 395728, 395729, G06F 1300

Patent

active

054737621

ABSTRACT:
A system for pipelining bus requests includes a bus, at least one node coupled to the bus, and a bus coordinator coupled to the node. The node uses a single bus request signal to both request control of the bus from the bus coordinator, and to retain control of the bus. In response to an asserted bus request signal from the node, the coordinator sends an asserted bus grant signal to the node to grant the node control of the bus. This bus grant signal tracks the bus request signal so that as long as the bus request signal remains asserted, the bus grant signal also is asserted. To allow for pipelining, the bus coordinator maintains the bus grant signal in an asserted state for at least one clock cycle after the bus request is deasserted. By holding the bus grant signal in the asserted state for one extra cycle, the coordinator gives the node time to deassert and then to reassert the bus request signal before the bus grant signal changes state. If the bus request is reasserted within the extra cycle, the coordinator continues to maintain the bus grant signal in the asserted state so that no state change is experienced by the bus grant signal between the deassertion and the reassertion of the bus request signal. In this manner, consecutive bus requests are pipelined. To further increase the efficiency of the system, the node deasserts the bus request signal at least one clock cycle before it send its last set of information, and continues to send information signals in the following clock cycle. By so doing, the node ensures that the extra clock cycle of the bus grant is not wasted.

REFERENCES:
patent: 5255376 (1993-10-01), Frank
patent: 5280623 (1994-01-01), Sodos et al.
patent: 5289583 (1994-02-01), Fischer et al.
Bergey, A. L. Jr. and Coale, J. L., "Method for Decreasing Arbitration Overhead", IBM Technical Disclosure Bulletin, vol. 26, No. 7A, Dec. 1983, pp. 3370-3371.
Blum, A., "Look-Ahead Access Request Circuit for Computer Systems", IBM Technical Disclosure Bulletin, vol. 22, No. 3, Aug. 1979, pp. 1059-1060.
"Processor Bus Arbitration With Dead Cycles," IBM Technical Disclosure Bulletin, vol. 32, No. 8A, Jan. 1990, p. 451.

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