Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Patent
1996-12-31
1999-06-29
Hoff, Marc S.
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
341122, H03M 112
Patent
active
059174404
ABSTRACT:
In accordance with the present invention, circuits are disclosed for use in implementing higher order sigma delta analog to digital conversion of narrowband signals with cascaded lower order circuit networks. The lower order circuit networks employ resonator circuits utilizing unit delay functional blocks to implement a specific transfer function. The unit delays are implemented utilizing sample and hold circuits operated by controlled switching of the circuit elements. In one embodiment, the resonator circuit includes a first sample and hold circuit for implementing a unit delay of corresponding input signals where the output of the first sample and hold circuit is coupled into a feedback loop with one or more additional sample and hold circuits for implementing a dual cascaded unit delay. The delayed signals from the feedback loop are then summed with the input signals at the input of the first sample and hold circuit. Advantageously, the present invention overcomes performance limitations of complex higher order sigma delta analog to digital converters that suffer from circuit nonidealities such as component mismatch, finite operational amplifier gain, bandwidth and design complexities associated with integrator based implementations. Alternate embodiments of the present invention include a switched capacitor based circuit for implementing the lower order delay function block based networks and a current copier or switched current approach. The switched capacitor circuit employs a first operational amplifier for inputting signals and summing with delayed samples of the input signals and a second operational amplifier coupled in a feedback loop with the first operational amplifier for implementing the delayed samples of the input signals. The switched current circuit employs a first current copier for sampling input signals and summing with a delay of the input signals. Second and third current copiers are used for implementing delayed sampling and holding for two separate signals output from the first current copier. The sampling, holding, delaying and summing are implemented with controlled switching in the circuits.
REFERENCES:
patent: 4268793 (1981-05-01), Amazawa et al.
patent: 4517518 (1985-05-01), Ishigaki
patent: 4590458 (1986-05-01), Evans et al.
patent: 4684922 (1987-08-01), Minogue
patent: 4994804 (1991-02-01), Sakaguchi
patent: 5392039 (1995-02-01), Thurston
patent: 5521599 (1996-05-01), McCarroll et al.
patent: 5608400 (1997-03-01), Pellon
patent: 5673044 (1997-09-01), Pellon
patent: 5682161 (1997-10-01), Ribner et al.
"Multibit Bandpass Delta-Sigma Modulators Using N-path Structures", by Schreir and B.R. Hong et al., IEEE International Symposium on Circuits & Systems, 1992.
"A 15b 30kHz Bandpass Sigma-Delta Modulator", by L. Longo et al., IEEE International Solid-State Circuits Conference, 1993.
"Multistage Bandpass Delta Sigma Modulators", by Ribner, IEEE Transactions on Circuits and Systems, 1994, discloses an architecture for oversampled delta sigma A/D converts.
Delta-Sigma Data Converters Chapter 9, by Norsworthy, Schreier and Temes, IEEE Press Marketing, 1996.
Hoff Marc S.
Jean-Pierre Peguy
Lucent Technologies - Inc.
LandOfFree
Implementing transmission zeroes in narrowband sigma-delta A/D c does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Implementing transmission zeroes in narrowband sigma-delta A/D c, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Implementing transmission zeroes in narrowband sigma-delta A/D c will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1379216