Single chip controller-memory device and a memory architecture a

Details Single chip controller-memory device and a memory architecture a Single chip controller-memory device and a memory architecture a

1994-05-09

1995-12-05

Nelms, David C.

Static information storage and retrieval

Addressing

36523002, 36523003, 36523006, 365 52, 365200, 345188, G11C 800, G06F 1520

Patent

active

054735734

ABSTRACT:
A processing device 107 is provided disposed on a single chip which includes a controller 103 and a memory 104. The controller 103 is coupled to an address bus 202 and a data bus 204. The memory 103 includes a plurality of independently addressable blocks 200 of memory cells, each block 200 coupled to the address bus 202 and having a selected number of output lines coupled to the data bus 204. The controller 103 accesses a location of the selected number of memory cells of a selected one of the blocks 200 through an address presented on the address bus 202.

REFERENCES:
patent: 5265231 (1993-11-01), Nuwayser
patent: 5278801 (1994-01-01), Dresser et al.
patent: 5287527 (1994-02-01), Delp et al.
patent: 5353402 (1994-10-01), Lau
patent: 5388073 (1995-02-01), Usami et al.
patent: 5388193 (1995-01-01), Pathak et al.
patent: 5426753 (1995-06-01), Moon

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