Method of reading data and read-only memory circuit

Details Method of reading data and read-only memory circuit Method of reading data and read-only memory circuit

1995-04-10

1995-12-05

Nelms, David C.

Static information storage and retrieval

Read only systems

Semiconductive

36518901, 36518909, G11C 1700, G11C 1712

Patent

active

054735602

ABSTRACT:
In a method of reading data comprising the steps of selecting a given column line and a bit line adjoining to the column line among a plurality of column lines (102-1.about.102-3) and bit lines (101-1, 101-2)based on column selection signals (Y.sub.1 .about.Y.sub.3), selecting a given row line among a plurality of row lines (103-1.about.103-n) based on row selection signals (X.sub.0 .about.X.sub.n) and reading out data which is stored in memory cells (104-01.about.104-n4) each of which is coupled to the given column line and the row line to the selected bit line, the given column line is set at a first potential level (a potential level supplied by a voltage regulator circuit 160) and almost at the same time the selected bit line is set at a second potential level (a potential level supplied by a sense amplifier circuit 150) which is lower than the first potential level and unselected column lines are set at a third potential level (ground potential level or a potential level supplied by the potential supply circuit 190) which is lower than the second potential level to read out data. As a result, it is possible to perform a high-speed data reading. Moreover, it is possible to realize low power consumption since there flows no useless current at a standby state.

REFERENCES:
patent: 4805143 (1989-02-01), Matsumoto
patent: 4811301 (1989-03-01), Houston
patent: 5020026 (1991-05-01), Schreck et al.
patent: 5132933 (1992-07-01), Schreck
patent: 5202848 (1993-04-01), Nakagawara

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