Relay-race FLL/PLL high-speed timing acquisition device

Details Relay-race FLL/PLL high-speed timing acquisition device Relay-race FLL/PLL high-speed timing acquisition device

1997-08-21

1999-06-29

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327163, 455210, 455260, H03L 706

Patent

active

059173513

ABSTRACT:
A relay-race FLL/PLL high-speed timing acquisition device according to the invention comprises a transition detector, a voltage controlled oscillator, a loop filter of PLL, a first lowpass filter, a 90.degree. phase shifter, a second lowpass filter, and a plurality of multipliers. In addition, this relay-race FLL/PLL high-speed timing acquisition device is characterized by further comprising a frequency delimiter which includes a highpass filter coupled to a first circuit, a second circuit coupled to the highpass filter, a third lowpass filter coupled to the second circuit, a Schmitt inverter coupled to the third lowpass filter, and a switch member coupled to the Schmitt inverter. The relay-race FLL/PLL high-speed timing acquisition device can obtain stable and high speed timing acquisition by means of the frequency delimiter.

REFERENCES:
patent: 5446418 (1995-08-01), Lin et al.

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