MIS device having lightly doped drain structure

Details MIS device having lightly doped drain structure MIS device having lightly doped drain structure

1989-08-31

1992-09-08

James, Andrew J.

357 239, 357 2311, 357 52, H01L 2910, H01L 2906, H01L 2934

Patent

active

051462915

ABSTRACT:
A MOS FET comprises a pair of source and drain impurity regions, a gate oxide film and a gate electrode. The source and drain regions have an LDD structure in which high concentration impurity regions and low concentration impurity regions are set off. The gate electrode is formed to extend over the channel region and contains sidewalls overlying the low concentration impurity regions. In addition, portions of the gate oxide film located between the sidewalls of the gate electrode and the respective low concentration impurity regions are formed to have a film thickness larger than that of the portion located between the gate electrode and the channel region. The thick portion of the oxide film underlying the gate sidewalls form a charge storage layer which reduces the resistance of the low impurity concentration region while minimizing the gate capacitance. In another example, conductive sidewall spacers are formed on sidewalls of a gate electrode through an insulating film. The sidewall spacers are connected with source and drain electrode connections or directly with source and drain impurity regions. Hot carriers generated near the drain are taken out from a gate insulating layer through conductive sidewall spacers. Accordingly, increase of the resistance due to trapped hot carriers can be prevented.

REFERENCES:
patent: 4727038 (1988-02-01), Watabe et al.
patent: 4952993 (1990-08-01), Okumura
patent: 4954867 (1990-09-01), Hosaka
patent: 4978628 (1990-12-01), Rosenthal
Paul J. Tsang et al "Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology", IEEE Transactions on Electron Devices, vol. EL-29, No. 4, Apr. 1982, pp. 590-596.
Ryuichi Izawa et al "The Impact of Gate-Drain Overlapped LDD (Gold) for Deep Submicron VLSI's ", IEEE Central Research Laboratory, Hitachi, Ltd., Kokubunju, Tokyo 1985, Japan, 1987, pp. 38-41.

Affiliated with

Also associated with

Rating

MIS device having lightly doped drain structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with MIS device having lightly doped drain structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MIS device having lightly doped drain structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-137854