Patent
1994-05-25
1995-12-26
Swann, Tod R.
395375, 395416, 3954211, G06F 1208
Patent
active
054796326
ABSTRACT:
A microcomputer includes a layered memory having a higher layer for storing a series of instructions forming a program to be executed by the microcomputer and a lower layer, having an upside layer accessed by ID information in the instructions stored in the higher layer memory, and a downside layer, accessed by the upside layer, having a sequence of storage locations storing code data for controlling the execution unit to calculate effective addresses.
REFERENCES:
patent: 4975837 (1990-12-01), Woodward et al.
Fujita Kouichi
Sato Fumiki
Mitsubishi Denki & Kabushiki Kaisha
Peikari J.
Swann Tod R.
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