High throughput extended-precision multiplier

Details High throughput extended-precision multiplier High throughput extended-precision multiplier

1985-06-19

1989-02-28

Harkcom, Gary V.

Boots, shoes, and leggings

364754, G06F 752

Patent

active

048092126

ABSTRACT:
A multiplier formed as a single integrated circuit chip generates in consecutive clock cycles the single-precision partial products of multiple-precision operands. Provision of an on-chip temporary register and "wrap-back" path avoids transmitting and externally storing intermediate results so that no clock cycles are used solely for data-transfers or other "overhead". Consecutive double-precision multiplications can be performed concurrently so that complete quadruple-precision products are generated every four cycles.

REFERENCES:
patent: 4574421 (1988-06-01), Bosshart
Chevillat et al, "Pipelined Hardware Multiplier with Extended Precision", IBM Technical Disclosure Bulletin, vol. 23, No. 9, 2/81, pp. 4322-4323.

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