Process for fabrication of an SRAM cell having a highly doped st

Details Process for fabrication of an SRAM cell having a highly doped st Process for fabrication of an SRAM cell having a highly doped st

1994-03-23

1995-12-05

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 47, 437 60, H01L 2170, H01L 2700

Patent

active

054728991

ABSTRACT:
An SRAM cell and a process for forming an SRAM cell comprises: forming a gate oxide layer on a semiconductor substrate, forming a gate on the gate oxide layer, forming a first ion implantation into the substrate in areas adjacent to the gate, performing a second ion implantation in an area immediately adjacent to the gate, depositing a dielectric layer over the gates, etching the dielectric layer to form a spacer structure therefrom, with the remainder of the dielectric layer being removed by the etching, and a third ion implantation in the substrate in all regions adjacent to the gates and the spacer forming more highly doped regions adjacent to the gate and the spacer.

REFERENCES:
patent: 4950617 (1990-08-01), Kumagai et al.
patent: 5057893 (1991-10-01), Sheng et al.
patent: 5198386 (1993-03-01), Gonzalez
patent: 5426065 (1995-06-01), Chan et al.
"A New Process Technology for a 4Mbit SRAM with Polysilicon Load Resistor Cell", K. Yuzuriha et al, Symposium on VLSI Technology, pp. 61-62 (1989).

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