Semiconductor integrated circuit chip

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays

Patent

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Details

257208, 257207, 257659, H01L 2710, H01L 3900

Patent

active

058922504

ABSTRACT:
There is provided a semiconductor integrated circuit chip including (a) a semiconductor substrate, (b) an insulating film formed on the semiconductor substrate, (c) first, second and third timing pulse signal lines each of which is formed of a common metal wiring layer and from which clock skew is generated, (d) an internal circuit to which the first, second and third timing pulse signal lines are electrically connected, (e) a first control signal line being designed to keep a high level while the internal circuit is in operation, and (f) a second control signal line being designed to keep a low level while the internal circuit is in operation. The second control line is disposed adjacent to and in parallel with one of sides of the first timing pulse signal line, the second timing pulse signal line is disposed adjacent to and in parallel with a side of the second control signal line at the opposite side of the first timing pulse signal line, the first control signal line is disposed adjacent to and in parallel with the other side of the first timing pulse signal line, and the third timing pulse signal line is disposed adjacent to and in parallel with a side of the first control signal line at the opposite side of the first timing pulse signal line. In the semiconductor integrated circuit chip, the first, second and third timing pulse signal lines are shielded with the first and second control signal lines to thereby reduce a time constant on signal transmission in the timing pulse signal lines, resulting in almost zero clock skew.

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