Fishing – trapping – and vermin destroying
Patent
1995-04-26
1995-12-05
Quach, T. N.
Fishing, trapping, and vermin destroying
437 44, 437235, 437236, 748DIG113, H01L 21336
Patent
active
054728908
ABSTRACT:
A LDD MOS transistor having a small fringe capacitance is fabricated by the steps of forming, lightly-doped source and drain regions by introducing impurities into a semiconductor substrate by using gate electrode as a mask, forming a pair of sidewall spacers above side surfaces of the gate electrode, forming heavily doped source and drain regions by an ion implantation method using the pair of sidewall spacers as a mask, removing the pair of sidewall spacers, and forming a pair of new sidewall spacers having a dielectric constant lower than that of silicon oxide above the side surface of the gate electrode, including the use of polyimide or boron nitride as the spacer material.
REFERENCES:
patent: 4753898 (1988-06-01), Parmllo et al.
patent: 4769686 (1988-09-01), Horiuchi et al.
patent: 4776922 (1988-10-01), Bhattacharyya et al.
patent: 4838991 (1989-06-01), Cote
patent: 4924279 (1990-05-01), Shimbo
patent: 5081559 (1992-01-01), Fazan et al.
patent: 5166096 (1992-11-01), Cote et al.
patent: 5324690 (1994-06-01), Gelatos et al.
Pfiester, J. R., "LDD MOSFET's Using Disposable Sidewall Spacer Technology", IEEE Elec. Dev. Lett., vol. 9, No. 4, Apr. 1988, pp. 189-192.
"Copper Multilevel Interconnections", IBM Tech. Disc. Bull., vol. 33, No. 11, Apr. 1991, pp. 299-300.
NEC Corporation
Quach T. N.
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