Method of fabricating semiconductor device having high-and low-v

Details Method of fabricating semiconductor device having high-and low-v Method of fabricating semiconductor device having high-and low-v

1993-11-09

1995-12-05

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 57, H01L 21265, H01L 2170, H01L 2700

Patent

active

054728878

ABSTRACT:
A semiconductor device (76) is provided with a high-voltage portion including NMOS transistor (78) and PMOS transistor (82b) and a low-voltage portion including NMOS transistor (80) and PMOS transistor 82(a). The high-voltage NMOS transistor (78) includes source/drain regions (90a, 90b) having N- regions (90a.sub.1, 90b.sub.1) that are self-aligned with a gate (78) and N+ regions (90a.sub.2, 90b.sub.2) that are self-aligned with sidewall spacers (91) formed on sidewalls of the gate (78) to improve reliability under continuous high voltage operating conditions. The low voltage NMOS transistor includes source/drain regions (92a, 92b) that are self-aligned with sidewall spacers (92) to permit channel lengths to be scaled to less than 2 microns. The low-voltage PMOS transistor (82a) and high-voltage PMOS transistor (82b) include source/drain regions (116a-116d) that are self-aligned with sidewall spacer extension regions (110a) formed over sidewall spacers (91) permitting low-voltage PMOS transistor channel lengths to be scaled to less than 2 microns.

REFERENCES:
patent: 4530150 (1985-07-01), Shirato
patent: 5023190 (1991-06-01), Lee et al.
patent: 5061649 (1991-10-01), Takenouchi et al.
patent: 5105252 (1992-04-01), Kim et al.
patent: 5278441 (1994-01-01), Kang et al.

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