Detector logic circuit for a sychronous transmission system for

Pulse or digital communications – Repeaters – Testing

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375 18, 341 57, H04L 300

Patent

active

048051900

ABSTRACT:
A detector logic circuit restores the value 0 or .+-.1 of a ternary symbol converted into a signal on five levels 0, .+-.1 and .+-.2 as a result of class 1, type n=2 partial response transmission. Employing only binary logic circuits, it is connected to the output of a comparator which has four thresholds and which delivers a value representing the receive level by four binary signals. Two of these signals indicate positive overshooting of extreme and intermediate positive thresholds. The other two indicate negative overshooting of negative extreme and intermediate thresholds. The circuit delivers the values of the ternary symbols detected in the form of two binary components which are available at the output and stored for the duration of a symbol by two flip-flops. Both are generated by combinational logic devices of similar design utilizing OR and NOR gates.

REFERENCES:
patent: Re30182 (1979-12-01), Howson
patent: 3388330 (1968-06-01), Kretzmer
patent: 3478267 (1969-11-01), Melas
patent: 4472813 (1984-09-01), Kolke et al.
patent: 4571734 (1986-02-01), Dolivo
patent: 4644564 (1987-02-01), Dolivo et al.

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