Semiconductor device having MOSFET and deep polycrystalline sili

Details Semiconductor device having MOSFET and deep polycrystalline sili Semiconductor device having MOSFET and deep polycrystalline sili

1987-06-22

1989-02-14

Laroche, Eugene R.

357 59, 357 47, 357 48, H01L 2702, H01L 2904

Patent

active

048050083

ABSTRACT:
A semiconductor device such as a CMOS is provided with highly doped polycrystalline silicon regions for preventing undesired operations of parasitic transistors. Each polycrystalline region is extended deeper from a top surface of the silicon chip than source and drain regions of MOS transistors. In a substrate region of each MOS, one polycrystalline region of the same conductivity type as the substrate region is formed near the source region, and connected with said source region so that the polycrystalline region is held equipotential with the source region.

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Kyomasu, et al, "Analysis of Latch-Up in CMOS IC," Denshi-Tsushin-Gakkai-Ronbunshi, '78/2 vol. J61-CN02, pp. 106-113.

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