Input/output control system and method for direct memory transfe

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364DIG1, 36424234, 364DIG2, 364940, 36494279, 395285, G06F 1300, G06F 1338

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054758602

ABSTRACT:
A digital data processing apparatus has two functional units (e.g., a host processing section and a peripheral device) and a controller for transferring information therebetween. The first functional unit generates a send message descriptor block ("MDB") signal specifying one or more addresses in an associated local memory from which data is to be transferred. The second functional unit generates a receive MDB signal specifying one or more locations in its associated local memory to which data is to be transferred. The controller matches send and receive MDB signals, particularly, those specifying the same logical or virtual channel. Once a match is found, the controller transfers data between the respective memory locations of the first and second functional units. A controller as described above transfers data between the host and peripheral processors by directly accessing data in their respective "memory spaces."

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NEC Electronics Inc., product information brochure for the uPD7281 Image Pipelined Processor, pp. 2-169-2-211.
Thorsten von Eicken et al., "Active Messages: a Mechanism for Integrated Communication and Computation", Report No. UCB/CSD 92/#675, Mar. 1992 Computer Science Division-EECS, University of California, Berkeley, Calif. 94720.

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