Patent
1994-08-17
1995-12-12
Downs, Robert W.
G06F 1518, G06G 760
Patent
active
054757940
ABSTRACT:
A semiconductor neural network includes a coupling matrix having coupling elements arranged in a matrix which couple with specific coupling strengths internal data input lines to internal data output lines. The internal data output lines are divided into groups. The neural network further comprises weighting addition circuits provided corresponding to the groups of the internal data output lines. A weighting addition circuit includes weighing elements for adding weights to signals on the internal data output lines in the corresponding group and outputting the weighted signals, and an addition circuit for outputting a total sum of the outputs of those weighting elements. The internal data output lines are arranged to form pairs and the addition circuit has a first input terminal for receiving one weighting element output of each of the pairs in common, a second input terminal for receiving the other weighting element output of each of the pairs in common, and a sense amplifier for differentially amplifying signals at the first and second input terminals. The neural network further includes a circuit for detecting a change time of an input signal, a circuit responsive to an input signal change for equalizing the first and second input terminals for a predetermined period, and a circuit for activating the sense amplifier after the equalization is completed. The information retention capability of each coupling element is set according to the weight of an associated weighting element. This neural network can provide multi-valued expression of coupling strength with less number of coupling elements.
REFERENCES:
patent: 4660166 (1987-04-01), Hopfield
patent: 4807168 (1989-02-01), Moopenn et al.
patent: 4901271 (1990-02-01), Graf
patent: 4982370 (1991-01-01), Matsumoto et al.
patent: 4988891 (1991-01-01), Mashiko
patent: 5004932 (1991-06-01), Nejime
patent: 5021988 (1991-06-01), Mashiko
patent: 5053638 (1991-10-01), Furutani et al.
patent: 5101361 (1992-03-01), Eberhardt
patent: 5146542 (1992-09-01), Engeler
DeGloria, "The VLSI Technology and the Design of Neural Networks", first Italian Workshop Parallel Architecture and Neural Networks, App. 1988, pp. 119-127.
Mead et al., "Analog VLSI Implementation of Neuralo Systems", Kluwer Academic Pub., 1989, pp. 135-169.
Schwartz, et al., "A Programmable Analog Neural Network Chip," IEEE Jour. Solid State Circuits, Apr. 1989, pp. 688-697.
Treleaven et al., "VLSI Architecture for Neuralo Networks," IEEE Micro, Dec. 1989, pp. 8-27.
Rossetto et al., "Analog VLSI Synoptic Matrices," IEEE Micro, Dec. 1989, pp. 56-63.
Alspector et al., "Performance of a Stochastic Learning Microchip", Advances in Neural Information Processing Systems I, 1989, pp. 748-760.
Graf et al. "Analog Electronic Neural Network Circuits," IEEE Circuit and Devices Mag, Jul. 1989, pp. 44-55.
Graf et al., "VLSI Implementation of a Neoral Network Model," Computer, Mar. 1988, pp. 41-49.
Alspector et al., "A Neuromorphic VLSI Learning System," Advanced Research in VLSI, 1987, pp. 313-349.
Graf, "A CMOS Assopciative Memory Chip Based on Neural Network," 87 ISSCC, Digest of Technical Papers, Feb. 1987, pp. 304-305.
Downs Robert W.
Mitsubishi Denki & Kabushiki Kaisha
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