Packet video signal inverse transport processor memory address c

Cryptography – Particular algorithmic function encoding – Nbs/des algorithm

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Details

3701101, 348384, 348441, 348409, H04N 7167

Patent

active

054757541

ABSTRACT:
In an inverse transport processor, program component packet payloads of respective program components are directed to select areas of random access memory (RAM) (18) in accordance with a plurality of start and end pointers which are stored in a first plurality (86, 89) of registers, one for each program component. Addresses are generated, in part, by a plurality of read pointer registers (82) multiplexed with an adder (80) to successively increment the pointers for respective program components. The start pointers are associated with read pointers to from memory addresses that scroll through designated memory blocks selectively assigned to respective program components. Memory access for read and write functions are arbitrated (98) so that no incoming program data can be lost, and all component processors are serviced.

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patent: 5239365 (1993-08-01), Uz
patent: 5289276 (1994-02-01), Siracusa et al.
patent: 5371547 (1994-12-01), Siracusa et al.

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