Multiplex communications – Wide area network – Packet switching
Patent
1993-07-12
1995-12-12
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
370 581, H04Q 1104
Patent
active
054756766
ABSTRACT:
First stage and third stage four-input four-output space division switches are arranged before and after a second stage time division switch, and two outputs of the first stage space division switch and two inputs of the third stage space division switch are connected by bypassing the time division switch. The time division switch has n control memories. A first control memory stores connection information in a normal state of each path set in the transmission line, a second control memory stores connection information of a first alternative path when failures occur in a path, and an n-th control memory (n is any integer equal or greater than 3) stores connection information of an (n-1)th alternative path, and a control memory corresponding the a failure pattern is selected from the n control memories for each path.
REFERENCES:
patent: 4392221 (1983-07-01), Hesketh
patent: 4543652 (1985-09-01), Amada et al.
patent: 5079761 (1992-01-01), Krumenacker et al.
4-Fiber BLSR Overview, Apr. 1, 1992.
Ashi Yoshihiro
Fujita Hiroyuki
Nakano Yukio
Takatori Masahiro
Hitachi , Ltd.
Olms Douglas W.
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