Fishing – trapping – and vermin destroying
Patent
1986-03-07
1989-02-14
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437200, 437192, 437 56, 437 48, 357 42, 148DIG20, 148DIG147, H01L 21283
Patent
active
048046361
ABSTRACT:
Disclosed is a process for making VLSI integrated circuits and a local interconnect system, wherein first poly, second poly and moat are all interconnected in any desired pattern by a TiN local interconnect. No masks are required beyond those which would be required for the two poly levels and local interconnect capability anyway.
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Groover, III Robert
Haken Roger A.
Holloway Thomas C.
Anderson Rodney M.
Hearn Brian E.
Heiting Leo N.
Quach T. N.
Sharp Melvin
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