Method and apparatus for enhanced EPROM and EEPROM programmabili

Details Method and apparatus for enhanced EPROM and EEPROM programmabili Method and apparatus for enhanced EPROM and EEPROM programmabili

1994-04-14

1996-02-20

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

G11C 700

Patent

active

054935261

ABSTRACT:
An EPROM or EEPROM employs an alternate voltage level of 2 volts replaces solid ground (0 volts) during programming and performs a `zero` logic level function. This `soft` zero of 2 volts is applied to bit lines not selected for programming. As a soft zero, this alternative voltage reduces internal voltage stresses and helps prevent field inversion and keep parasitic field transistors between bit lines shut off. By reducing internal voltage stresses on gate oxides, and by helping prevent field inversion, the use of a soft zero voltage allows smaller circuit architectures to be designed for a given high programming voltage.

REFERENCES:
patent: 4888734 (1989-12-01), Lee et al.
patent: 4939690 (1990-07-01), Momodomi et al.
patent: 5088060 (1992-02-01), Endoh et al.
patent: 5172388 (1992-12-01), Mehrotra et al.

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