Delay circuit

Details Delay circuit Delay circuit

1988-02-12

1990-04-03

Heyman, John S.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307451, 307585, H03K 513, H03K 17284, H03K 1730

Patent

active

049143263

ABSTRACT:
A delay circuit having a complementary insulated gate device comprises an inverter (10) having a series connection of a p type field effect transistor Q3 and an n type field effect transistor Q4 and a transmission gate (20) having a parallel connection of a p type field effect transistor Q1 and an n type field effect transistor Q2 connected to the preceding stage of the inverter (10), and the gates of the transistors Q1 and Q2 are connected together to an output terminal (3). The logical threshold voltage of the inverter (10) is set at a higher value in the range of the input voltage of the inverter (10). There is a peculiar period in which the transistors Q1 and Q2 of the transmission gate (20) transmit only a little increase of the input voltage to the inverter (10) during the increase of the input voltage. Due to the existence of this peculiar period, this circuit outputs a delayed output signal only when the input voltage increases. In addition, the rise time and fall time of the output signal are short.

REFERENCES:
patent: 4571504 (1986-02-01), Iwamoto et al.
patent: 4603264 (1986-07-01), Nakano
patent: 4703201 (1987-10-01), McGrail

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