Synchronizing circuit

Details Synchronizing circuit Synchronizing circuit

1988-10-07

1990-04-03

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307595, 307480, 307516, 307269, 3072721, 328 63, H03K 3013, H03K 3027, H03K 19003, H03K 505

Patent

active

049143255

ABSTRACT:
A circuit for synchronizing data pulses, comprises a D-type flip-flop and a set-reset type flip-flop. The D-type flip-flop is enabled by a system clock pulse train wherein the D-type flip flop conducts to product an output at a time controlled by the system clock pulse train if a data pulse is present, thereby synchronizing the data pulse with the system clock. The set-reset flip-flop is enabled by a second clock pulse train which lags after the system clock pulse train. The lag period is long enough to suppress transient conditions counsel by the leading edges of the system clock pulses. The set-reset flip-flop drives the D-type flip-flop.

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patent: 4771441 (1988-09-01), Spengler et al.
patent: 4797574 (1989-01-01), Okubo et al.
McGuire, "A Simple Synchronizing Circuit", IBM Technical Disclosure Bulletin, vol. 3, No. 9, Feb. 1961.

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