Reduced mask process for manufacture of MOS gated devices

Details Reduced mask process for manufacture of MOS gated devices Reduced mask process for manufacture of MOS gated devices

1995-02-17

1995-12-12

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 27, 437 29, 437148, 437931, 148DIG126, H01L 21265

Patent

active

054749468

ABSTRACT:
A process for forming a MOS gated device in which an oxide layer is patterned to have adjacent thick and thin oxide layers atop a silicon surface. Polysilicon is then patterned atop the oxide layer with a critical alignment step to the thin oxide layers in the process. Boron is implanted through both the thick and thin regions of the oxide which are exposed by the polysilicon mask to form P type base regions and P type guard rings in the silicon. Arsenic is thereafter implanted at an energy at which arsenic atoms penetrate only the thin oxide exposed by the polysilicon to form self-aligned source regions in the base regions previously formed. A contact opening mask which is critically aligned to the polysilicon mask forms openings for making contact to the silicon. The device is completed using non-critical alignment masking steps.

REFERENCES:
patent: 4902636 (1990-02-01), Akiyama et al.
patent: 5024962 (1991-06-01), Murray et al.
patent: 5030581 (1991-07-01), Yakushiji et al.

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