Process for manufacturing integrated circuit with power field ef

Details Process for manufacturing integrated circuit with power field ef Process for manufacturing integrated circuit with power field ef

1992-12-07

1995-12-12

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

257346, 437979, 148DIG126, H01L 21234

Patent

active

054749441

ABSTRACT:
A manufacturing process for an integrated circuit which includes at least one vertical-current-flow MOS transistor. The patterned photoresist which screens the body implant is also used to mask the etching of a nitride layer over a pad oxide. After the photoresist is cleared, the nitride pattern is transferred into the oxide, and the resulting oxide
itride stack is used to mask the source implant. The nitride/oxide stack is then removed, the gate oxide is grown, and the gate layer is then deposited.

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patent: 4757032 (1988-07-01), Contiero
patent: 4890142 (1989-12-01), Tonnel et al.
patent: 4920064 (1990-04-01), Whight
patent: 4998151 (1991-03-01), Korman et al.
patent: 5055895 (1991-10-01), Akiyama et al.
patent: 5081052 (1992-01-01), Kobayashi et al.
Wolf, S. "Silicon Processing for the VLSI Era", Lattice Press Sunset Beach, Calif., vol. 2 pp. 298-301.

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