Memory address translation system having modifiable and non-modi

Details Memory address translation system having modifiable and non-modi Memory address translation system having modifiable and non-modi

1991-09-26

1993-10-19

Kulik, Paul V.

Boots, shoes, and leggings

395400, 364DIG1, 364243, 3642434, 36424341, 3642563, 3642564, G06F 1210

Patent

active

052553841

ABSTRACT:
A Cache-Memory Management System provides high speed virtual to real address translation. Address translation logic, comprised of mutually exclusive modifiable and nonmodifiable translation logic, selectively provides real address output responsive to the externally supplied virtual address from the processor. The modifiable translation logic includes modifiable read-write memory, while the non-modifiable translation logic includes fixed combinational logic for providing predefined translations of predetermined virtual addresses to real addresses. A controller selectively accesses main memory on cache memory misses to load translation information and other data from main memory to the cache memory. In a preferred embodiment, the address translation logic provides an associated system tag defining access priorities and access modes with each address translation.

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