Interface for arbitrating access to the paging unit of a compute

Details Interface for arbitrating access to the paging unit of a compute Interface for arbitrating access to the paging unit of a compute

1992-10-15

1993-10-19

Heckler, Thomas M.

Boots, shoes, and leggings

364DIG1, 3642427, 3642543, 3642631, G06F 930

Patent

active

052553779

ABSTRACT:
An arrangement in a microprocessor having both a segmentation addressing scheme and a page mode addressing scheme which arrangement reviews requests for use of the paging unit, determines whether a request has been sent by the different units, and allows access to the bus for a request by the segmentation unit if the bus is not in use, allows access to the bus for a request by the prefetch unit if the bus is not in use and a request is not also outstanding from the segmentation unit, and provides for reentering requests to use the bus which are started but not completed when submitted.

REFERENCES:
patent: 4375639 (1983-03-01), Johnson, Jr.
patent: 4384323 (1983-05-01), Ahuja
patent: 4546431 (1985-10-01), Horvath
patent: 4646232 (1987-02-01), Chang et al.
patent: 4648029 (1987-03-01), Cooper et al.
patent: 4654777 (1987-03-01), Nakamura
patent: 4800490 (1989-01-01), Tanaka et al.
patent: 4837682 (1989-06-01), Culler
patent: 4870704 (1989-09-01), Matelan et al.
patent: 4972338 (1990-11-01), Crawford et al.
patent: 4989138 (1991-01-01), Radochonski

Affiliated with

Also associated with

Rating

Interface for arbitrating access to the paging unit of a compute does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interface for arbitrating access to the paging unit of a compute, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interface for arbitrating access to the paging unit of a compute will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1359008